Project Development in XILINX ISE 10.1

disgorge Development in XILINX ISE 10.1Chapter 4VHDL INTRODUCTIONA intention engineer in electronic industry uses hardw ar interpretation language to keep pace with the productivity of the competitors. With VHSIC (Very High run co-ordinated Circuits) ironware Description Language (VHDL) we fire quickly describe and compound circuits of several thousand gates. In admission VHDL provides the capabilities described as followsPower and flexibilityVHDL has powerful language constructs with which to save succinct code description of complex control logic. It in like manner has sixfold levels of pieceation description for controlling creation implementation. It supports rule libraries and creation of recycl commensurate comp onenessnts. It provides fancy hierarchies to create modular designs. It is one language fort design and simulation.Device Independent designVHDL permits to create a design without having to scratch choose a device foe implementation. With one design description, we potbelly sign many device computer architectures. Without being familiar with it, we rump hone our design for re line or performance. It permits multiple style of design description.Por birth control pillilityVHDL portability permits to dissemble the same design description that we suck up synthesized. Simulating a large design description before synthesizing hatful save considerable time. As VHDL is a standard, design description groundwork be taken from one simulator to another, one tax deduction tool to another one platform to another-means description rouse be used in multiple regorges.Benchmarking capabilitiesDeviceindependent design and portability allows judicial systemmarking a design using different device architectures and different synthesis tool. We can take a complete design description and synthesize it, create logic for it, evaluate the results and finally choose the device-a Complex Programmable system of logic Device (CPLD) or a Field Pr ogrammable Gate Array (FPGA) that fits our requirements.ASIC MigrationThe capacity that VHDL generates, allows our product to hit the market quickly if it has been synthesized on a CPLD or FPGA. When production value reaches appropriate levels, VHDL facilitates the development of Application Specific Integrated Circuit (ASIC). Sometimes, the exact code used with the Programmable Logic Device (PLD) can be used with the ASIC and because VHDL is a well-defined language, we can be certified that out ASIC vendor leave deliver a device with evaluate functionality.4.1 VHDL DESCRIPTIONIn the search of a standard design and musical accompaniment for the Very High Speed Integrated Circuits (VHSIC) program, the United States Department of vindication (DOD) in 1981sponsored a workshop on Hardware Description Languages (HDL) at Woods Hole, Massachusetts. In 1983, the DOD established requirements for a standard VHSIC Hardware Description Language VHDL, its environment and its software was a warded to IBM, Texas Instruments and Intermetrics corporations.VHDL 2.0 was released only after the project was begun. The language was significantly improved correcting the shortcoming of the earlier versions VHDL 6.0 was released in 1984. VHDL 1078/1164 formally became the IEEE standard Hardware Description Language in 1987.A VHDL design is defined as an entity solvent and as an associated architecture body. The declaration specifies its interface and is used by architecture bodies of design entities at speeding levels of hierarchy. The architecture body describes the operation of a design entity by specifying its interconnectedness with other design entities structural description, by its behaviour behavioural description, or by a mixture of both. The VHDL language groups, sub programs or design entities by use of packages.For customizing generic descriptions of design entities, configurations are used. VHDL also supports libraries and contains constructs for accessing packages , design entities or configurations from various libraries.4.2 INTRODUCTION TO XILINX ISE 10.1 micturate a pertly Project bring to pass a new ISE project which bequeath target the FPGA device on the Spartan-3 Startup Kit demo board.To create a new projectSelect File new-made Project The spic-and-span Project Wizard appears.Type tutorial in the Project stir field.Enter or browse to a location (directory path) for the new project. A tutorial subdirectory iscreated automatically.Verify that HDL is filmed from the Top-Level artificial lake Type list.Click neighboring to move to the device properties page.Fill in the properties in the table as shown on a lower floorProduct Category AllFamily Spartan3Device XC3S200Package FT256Speed Grade -4Top-Level Source Type HDLSynthesis Tool XST (VHDL/Verilog)Simulator ISE Simulator (VHDL/Verilog) pet Language Verilog (or VHDL)Verify that Enable Enhanced Design Summary is selected. pay the default values in the remaining fields.When the tabl e is complete, your project properties pass on look like the following7. Click Next to proceed to the Create New Source window in the New Project Wizard. Atthe end of the next section, your new project will be complete.Create an HDL SourceIn this section, you will create the top-level HDL cross- shoot for your design. Determine the language that you wish to use for the tutorial. Then, continue either to the Creating aVHDL Source section below, or skip to the Creating a Verilog Source section.Creating a VHDL SourceCreate a VHDL source file for the project as followsClick the New Source button in the New Project Wizard.Select VHDL Module as the source type.Type in the file name previse.Verify that the Add to project silicon chipbox is selected.Click Next.Declare the ports for the counter design by filling in the port information as shown below7. Click Next, then Finish in the New Source Wizard Summary duologue box to complete thenew source file template.8. Click Next, then Next , then Finish.The source file containing the entity/architecture pair give aways in the Workspace, and the counter displays in the Source tab, as shown belowChecking the Syntax of the New Counter ModuleWhen the source files are complete, check the syntax of the design to find errors and typos.Verify that Implementation is selected from the drop-down list in the Sources window.Select the counter design source in the Sources window to display the related physical processes inthe Processes window.Click the + next to the Synthesize-XST process to expand the process group.Double- tattle the Check Syntax process.Note You must correct any errors found in your source files. You can check for errors in theConsole tab of the Transcript window. If you continue without valid syntax, you will not be able to simulate or synthesize your design.5. Close the HDL file.Design excuseVerifying Functionality using behavioral SimulationCreate a try bench wave form containing input stimulus you can u se to master the functionality of the counter module. The test bench waveform is a graphical put one over of a test bench.Create the test bench waveform as follows1. Select the counter HDL file in the Sources window.2. Create a new test bench source by selecting Project New Source.3. In the New Source Wizard, select Test Bench waver Form as the source type, and typeCounter_tbw in the File identify field.4. Click Next.5. The Associated Source page shows that you are associating the test bench waveformwith the source file counter. Click Next.6. The Summary page shows that the source will be added to the project, and it displaysthe source directory, type, and name. Click Finish.7. You need to set the clock frequency, setup time and sidetrack delay times in the Initialize.Timing dialog box before the test bench waveform editing window opens.The requirements for this design are the followingThe counter must operate justly with an input clock frequency = 25 MHz.The anxiety input will be valid 10 ns before the rising molding of CLOCK.The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK.The design requirements correspond with the values below.Fill in the fields in the Initialize Timing dialog box with the following information measure High Time 20 ns.Clock Low Time 20 ns.Input frame-up Time 10 ns.Output Valid clutch 10 ns.Offset 0 ns.Global signal GSR(FPGA).Note When GSR(FPGA) is enabled, degree centigrade ns. is added to the Offset value automatically. 8. Click Finish to complete the timing initialization.9. The unappeasable shaded areas that precede the rising edge of the CLOCK correspond to the InputSetup Time in the Initialize Timing dialog box. Toggle the DIRECTION port to define theinput stimulus.Note For more accurate alignment, you can use the Zoom In and Zoom Out toolbarbuttons.10. Save the waveform.11. In the Sources window, select the Behavioral Simulation view to see that the test benchwaveform file is automatically added t o your project.12. Close the test bench waveform.Simulating Design FunctionalityVerify that the counter design functions as you expect by playing behavior simulationas follows1. Verify that Behavioral Simulation and counter_tbw are selected in the Sourceswindow.2. In the Processes tab, click the + to expand the Xilinx ISE Simulator process anddouble-click the Simulate Behavioral Model process.The ISE Simulator opens and runs the simulation to the end of the test bench.3. To view your simulation results, select the Simulation tab and zoom in on the transitions.Note You can ignore any rows that start with TX.4. Verify that the counter is counting up and down as expected.5. Close the simulation view. If you are prompted with the following message, You have anactive simulation open. Are you sure you want to close it? click Yes to continue.You have now completed simulation of your design using the ISE Simulator.